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lt 3071 1 3071fc for more information www.linear.com/lt3071 applications n fpga and dsp supplies n asic and microprocessor supplies n servers and storage devices n post buck regulation and supply isolation typical application description 5a, low noise, programmable output, 85mv dropout linear regulator with analog margining the lt ? 3071 is a low voltage, ultrafast? transient re- sponse linear regulator. the device supplies up to 5 a of output current with a typical dropout voltage of 85 mv. a 0.01 f reference bypass capacitor decreases output voltage noise to 25 v rms . the lt3071?s high bandwidth permits the use of low esr ceramic capacitors, saving bulk capacitance and cost. the lt3071?s features make it ideal for high performance fpgas, microprocessors or sensitive communication supply applications. output voltage is digitally selectable in 50 mv increments over a 0.8 v to 1.8 v range. an analog margining function allows the user to adjust system output voltage over a continuous 10% range. the ic incorporates a unique tracking function to control a buck regulator powering the lt3071?s input. this tracking function drives the buck regulator to maintain the lt3071?s input voltage to v out + 300mv, minimizing power dissipation. internal protection includes uvlo, reverse - current protec - tion, precision current limiting with power foldback and thermal shutdown. the lt3071 regulator is available in a thermally enhanced 28- lead , 4 mm 5 mm qfn package. 0.9v, 5a regulator features n output current: 5a n dropout voltage: 85mv typical n digitally programmable v out : 0.8v to 1.8v n analog output margining: 10% range n low output noise: 25v rms (10hz to 100khz) n parallel multiple devices for 10a or more n precision current limit: 20% n output current monitor: i mon = i out /2500 n 1% accuracy over line, load and temperature n stable with low esr ceramic output capacitors (15f minimum) n high frequency psrr: 30db at 1mhz n enable function turns output on/off n vioc pin controls buck converter to maintain low power dissipation and optimize ef?ciency n pwrgd/uvlo/thermal shutdown flag n current limit with foldback protection n thermal shutdown n 28-lead (4mm 5mm 0.75mm) qfn package dropout voltage l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. ultrafast and vldo are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. output current (a) 0 dropout voltage (mv) 90 120 150 4 3071 ta01b 60 30 0 1 2 3 5 v out = 1.8v v bias = 3.3v v out = 0.8v v bias = 2.5v v in = v out(nominal) bias 50k lt3071 inen v o0 v o1 330f 2.2f 2.2f* 0.01f 1k *x5r or x7r capacitors 1nf nc 4.7f* 3071 ta01a 10f* pwrgd v out 0.9v5a v mon 2v at 5a full scale v o2 marga vioc sense out v bias 2.2v to 3.6v v in 1.2v pwrgd ref/byp i mon gnd downloaded from: http:///
lt 3071 2 3071fc for more information www.linear.com/lt3071 in , out ..................................................... ?0.3 v to 3.3 v bias ............................................................. ?0.3 v to 4v v o2 , v o1 , v o0 inputs .................................... ?0.3 v to 4v marga input ............................................... ?0.3 v to 4v en input ....................................................... ?0.3 v to 4v sense input ................................................. ?0.3 v to 4v vioc , pwrgd , i mon outputs ....................... ?0.3 v to 4v ref / byp output ........................................... ?0.3 v to 4v output short - circuit duration .......................... indefinite operating junction temperature ( note 2) lt 3071 e/ lt 3071 i .............................. ?40 c to 125 c lt 3071 mp ......................................... ?55 c to 125 c storage temperature range .................. ?65 c to 150 c (note 1) 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 vioc pwrgd ref/byp gnd inin in in margai mon gndsense out out out out enbias gnd v o2 v o1 v o0 gndgnd gnd gnd gnd gnd 7 17 18 19 20 21 2216 8 15 t jmax = 125c, ja = 30c/w to 35c/w exposed pad (pin 29) is gnd, must be soldered to pcb order information pin configuration absolute maximum ratings lead free finish tape and reel part marking* package description temperature range lt3071eufd#pbf lt3071eufd#trpbf 3071 28-lead (4mm 5mm) plastic qfn ?40c to 125c lt3071iufd#pbf lt3071iufd#trpbf 3071 28-lead (4mm 5mm) plastic qfn ?40c to 125c lt3071mpufd#pbf lt3071mpufd#trpbf 3071 28-lead (4mm 5mm) plastic qfn ?55c to 125c lead based finish tape and reel part marking* package description temperature range lt3071eufd lt3071eufd#tr 3071 28-lead (4mm 5mm) plastic qfn ?40c to 125c lt3071iufd lt3071iufd#tr 3071 28-lead (4mm 5mm) plastic qfn ?40c to 125c lt3071mpufd lt3071mpufd#tr 3071 28-lead (4mm 5mm) plastic qfn ?55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units in pin voltage range v in v out + 150mv, i out = 5a l 0.95 3.0 v bias pin voltage range (note 3) l 2.2 3.6 v regulated output voltage v out = 0.8v, 10ma i out 5a, 1.05v v in 1.25v v out = 0.9v, 10ma i out 5a, 1.15v v in 1.35v v out = 1v, 10ma i out 5a, 1.25v v in 1.45v v out = 1.1v, 10ma i out 5a, 1.35v v in 1.55v v out = 1.2 v , 10 ma i out 5 a , 1.45 v v in 1.65 v , v bias = 3.3 v v out = 1.5 v , 10 ma i out 5 a , 1.75 v v in 1.95 v , v bias = 3.3 v v out = 1.8 v , 10 ma i out 5 a , 2.05 v v in 2.25 v , v bias = 3.3 v l l l l l l l 0.792 0.891 0.990 1.089 1.188 1.485 1.782 0.800 0.900 1.000 1.100 1.200 1.500 1.800 0.808 0.909 1.010 1.111 1.212 1.515 1.818 v v v v v v v electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. c out = 15f (note 9), v in = v out + 0.3v (note 5), v bias = 2.5v unless otherwise noted. downloaded from: http:///
lt 3071 3 3071fc for more information www.linear.com/lt3071 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. c out = 15f (note 9), v in = v out + 0.3v (note 5), v bias = 2.5v unless otherwise noted. parameter conditions min typ max units regulated output voltage margining (note 3) marga = 1.2v marga = 0v l l 9.5 ?10.5 10 ?10 10.5 ?9.5 % % line regulation to v in v out = 0.8v, ? v in = 1.05v to 2.7v, v bias = 3.3v, i out = 10ma v out = 1.8v, ?v in = 2.05v to 2.7v, v bias = 3.3v, i out = 10ma l l 1.0 1.0 mv mv line regulation to v bias v out = 0.8v, ?v bias = 2.2v to 3.6v, v in = 1.1v, i out = 10ma v out = 1.8v, ?v bias = 3.25v to 3.6v, v in = 2.1v, i out = 10ma l l 2.0 1.0 mv mv load regulation, ?i out = 10ma to 5a v bias = 2.5v, v in = 1.05v, v out = 0.8v l ?1.5 ?3.0 ?5.5 mv mv v bias = 2.5v, v in = 1.25v, v out = 1.0v l ?2 ?4.0 ?7.5 mv mv v bias = 3.3v, v in = 1.45v, v out = 1.2v l ?2 ?4.0 ?7.5 mv mv v bias = 3.3v, v in = 1.75v, v out = 1.5v l ?2.5 ?5.0 ?9.0 mv mv v bias = 3.3v, v in = 2.05v, v out = 1.8v l ?3 ?7.0 ?13 mv mv dropout v oltage, v in = v out(nominal) (note 6) i out = 1a, v out = 1v l 20 35 mv i out = 2.5a, v out = 1v l 50 65 85 mv mv i out = 5a, v out = 1v l 85 120 150 mv mv sense pin current v in = 1.1v, v sense = 0.8v v bias = 3.3v, v in = 2.1v, v sense = 1.8v l l 35 200 50 300 65 400 a a ground pin current, v in = 1.3v, v out = 1v i out = 10ma i out = 5a l l 0.65 0.9 1.1 1.35 1.8 2.3 ma ma bias pin current in nap mode en = low l 120 200 320 a bias pin current, v in = 1.3v, v out = 1v i out = 10ma i out = 100ma i out = 500ma i out = 1a i out = 2.5a i out = 5a l l l l l l 0.75 1.25 2.0 2.6 3.5 4.5 1.08 1.8 3.0 3.8 5.2 6.9 1.5 2.4 4.0 5.0 7.0 10.0 ma ma ma ma ma ma current limit (note 5) v in ? v out < 0.3v, v bias = 3.3v v in ? v out = 1.0v, v bias = 3.3v v in ? v out = 1.7v, v bias = 3.3v l l l 5.1 3.2 1.2 6.4 4.5 2.5 7.7 5.8 4.3 a a a i mon full - scale output current ( note 3) i out = 5a, v in ? v out = 0.3v, v out = 0.8v, 1.8v l 1.6 2.0 2.4 ma i mon /i out scale (note 3) 1a i out 5a, v in ? v out = 0.3v, v out = 0.8v, 1.8v l 340 400 460 a/a reverse output current (note 8) v in = 0v, v out = 1.8v l 300 450 a pwrgd v out threshold percentage of v out(nominal) , v out rising percentage of v out(nominal) , v out falling l l 87 82 90 85 93 88 % % pwrgd v ol i pwrgd = 200a (fault condition) l 50 150 mv v bias undervoltage lockout v bias rising v bias falling l l 1.1 0.9 1.55 1.4 2.1 1.7 v v v in -v out servo voltage by vioc l 250 300 350 mv vioc output current v in = v out(nominal) + 150mv, sourcing out of the pin v in = v out(nominal) + 450mv, sinking into the pin l l 160 170 235 255 310 340 a a v il input threshold (logic-0 state), v o2 , v o1 , v o0 input falling l 0.25 v downloaded from: http:///
lt 3071 4 3071fc for more information www.linear.com/lt3071 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. c out = 15f (note 9), v in = v out + 0.3v (note 5), v bias = 2.5v unless otherwise noted. parameter conditions min typ max units v iz input range (logic-z state), v o2 , v o1 , v o0 l 0.75 v bias ? 0.9 v v ih input threshold (logic-1 state), v o2 , v o1 , v o0 input rising l v bias ? 0.25 v input hysteresis (both thresholds), v o2 , v o1 , v o0 60 mv input current high, v o2 , v o1 , v o0 v ih = v bias = 2.5v, current flows into pin l 25 40 a input current low, v o2 , v o1 , v o0 v il = 0v, v bias = 2.5v, current flows out of pin l 25 40 a en pin threshold v out = off to on, v bias = 2.5v v out = on to off, v bias = 2.5v v out = off to on, v bias = 2.2v to 3.6v v out = on to off, v bias = 2.2v to 3.6v l l l l 0.9 0.36 v bias 1.4 0.56 v bias v v v v en pin logic high current v en = v bias = 2.5v l 2.5 4.0 6.5 a en pin logic low current v en = 0v l 0.1 a v bias ripple rejection v bias = v out + 1.5v avg , v ripple =0.5v p-p , f ripple = 120hz, v in ? v out = 300mv, i out = 2.5a 75 db v in ripple rejection (notes 3, 4, 5) v bias = 2.5v, v ripple = 50mv p-p , f ripple = 120hz, v in ? v out = 300mv, i out = 2.5a 66 db reference voltage noise (ref/byp pin) c ref/byp = 10nf, bw = 10hz to 100khz 10 v rms output voltage noise v out = 1v, i out = 5a, c ref/byp = 10nf, c out = 15f, bw = 10hz to 100khz 25 v rms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3071 regulators are tested and specified under pulse load conditions such that t j ? t a . the lt3071e is 100% tested at t a = 25c. performance at ?40c and 125c is assured by design, characterization and correlation with statistical process controls. the lt3071i is guaranteed over the ?40c to 125c operating junction temperature range. the lt3071mp is 100% tested and guaranteed over the ?55c to 125c operating junction temperature range. note 3: to maintain proper performance and regulation, the bias supply voltage must be higher than the in supply voltage. for a given v out , the bias voltage must satisfy the following conditions: 2.2v v bias 3.6v and v bias (1.25 v out + 1v). for v out 0.95v, the minimum bias voltage is limited to 2.2v.note 4: operating conditions are limited by maximum junction temperature. the regulated output voltage specification does not apply for all possible combinations of input voltage and output current. when operating at maximum output current, limit the input voltage range to v in < v out + 500mv. note 5: the lt3071 incorporates safe operating area protection circuitry. current limit decreases as the v in -v out voltage increases. current limit foldback starts at v in ? v out > 500mv. see the typical performance characteristics for a graph of current limit vs v in ? v out voltage. the current limit foldback feature is independent of the thermal shutdown circuity. note 6: dropout voltage, v do , is the minimum input to output voltage differential at a specified output current. in dropout, the output voltage equals v in ? v do . note 7: gnd pin current is tested with v in = v out(nominal) + 300mv and a current source load. vioc is a buffered output determined by the value of v out as programmed by the v o2 -v o0 pins. vioc?s output is independent of the margining function.note 8: reverse output current is tested with the in pins grounded and the out + sense pins forced to the rated output voltage. this is measured as current into the out + sense pins . note 9: frequency compensation: the lt3071 must be frequency compensated at its out pins with a minimum c out of 15f configured as a cluster of (15) 1f ceramic capacitors or as a graduated cluster of 10f/4.7f/2.2f ceramic capacitors of the same case size. linear technology only recommends x5r or x7r dielectric capacitors. downloaded from: http:///
lt 3071 5 3071fc for more information www.linear.com/lt3071 typical performance characteristics dropout voltage vs v bias output voltage (0.8v) vs temperature dropout voltage vs i out dropout voltage vs temperature dropout voltage vs temperature dropout voltage vs temperature output voltage (1v) vs temperature output voltage (1.2v) vs temperature output voltage (1.5v) vs temperature output current (a) 0 dropout voltage (mv) 90 120 150 4 3071 g01 60 30 0 1 2 3 5 v out = 1.8v v bias = 3.3v v out = 0.8v v bias = 2.5v v in = v out(nominal) t j = 25c temperature (c) 0 dropout voltage (mv) 10 20 30 5 15 25 ?25 25 75 125 3071 g02 175 ?50 ?75 0 50 100 150 v in = v out(nominal) i out = 1a v out = 1.8v, v bias = 3.3v v out = 0.8v, v bias = 2.5v v out = 1.2v, v bias = 3.3v temperature (c) ?75 dropout voltage (mv) 60 80 100 125 3071 g03 4020 50 70 9030 10 0 ?25 ?50 25 0 75 100 150 50 175 v in = v out(nominal) i out = 2.5a v out = 1.8v, v bias = 3.3v v out = 0.8v, v bias = 2.5v v out = 1.2v, v bias = 3.3v temperature (c) ?75 dropout voltage (mv) 90 120 150 125 3071 g04 60 30 0 ?50 ?25 0 25 50 75 100 150 175 v in = v out(nominal) i out = 5a v out = 1.8v, v bias = 3.3v v out = 0.8v, v bias = 2.5v v out = 1.2v, v bias = 3.3v bias voltage (v) 2.2 0 dropout voltage (mv) 20 60 80 100 200140 2.6 3.0 3.2 3071 g05 40 160 180120 2.4 2.8 3.4 3.6 out = 1.8vout = 1.5v out = 0.8v i out = 5a t j = 25c temperature (c) ?75 output voltage (v) 0.808 0.8060.804 0.802 0.800 0.798 0.796 0.794 0.792 125 3071 g06 ?25 25 75 175 100 ?50 0 50 150 i load = 10ma temperature (c) ?75 output voltage (v) 1.002 1.006 1.010 125 3071 g07 0.9980.994 1.000 1.004 1.0080.996 0.992 0.990 ?25 ?50 25 0 75 100 150 50 175 i load = 10ma temperature (c) 1.188 output voltage (v) 1.196 1.204 1.2121.192 1.200 1.208 ?25 25 75 125 3071 g08 175 ?50 ?75 0 50 100 150 i load = 10ma temperature (c) 1.485 output voltage (v) 1.495 1.505 1.5151.490 1.500 1.510 ?25 25 75 125 3071 g09 175 ?50 ?75 0 50 100 150 i load = 10ma downloaded from: http:///
lt 3071 6 3071fc for more information www.linear.com/lt3071 output current (a) 0 0 gnd pin current (ma) 0.5 1.0 1.5 2.0 2.5 3.0 1 2 3 4 3071 g11 5 v out = 1.8v, v bias = 3.3v v out = 1.2v, v bias = 3.3v v out = 0.8v, v bias = 2.5v v in = v out + 300mv t j = 25c typical performance characteristics bias pin current in nap mode bias pin current vs i out gnd pin current vs i out ref/byp pin voltage vs temperature bias pin undervoltage lockout threshold output voltage (1.8v) vs temperature pwrgd threshold voltage pwrgd v ol vs temperature temperature (c) ?75 1.782 output voltage (v) 1.786 1.794 1.798 1.802 75 100 125 150 1.818 3071 g10 1.790 ?50 ?25 0 25 50 175 1.806 1.810 1.814 i load = 10ma temperature (c) 594 ref/byp voltage (mv) 598 602 606 596 600 604 ?25 25 75 125 3071 g12 175 ?50 ?75 0 50 100 150 c ref/byp = 0.01f temperature (c) ?75 bias pin current (a) 400350 300 250 200 150 100 50 0 125 3071 g13 ?25 25 75 175 100 ?50 0 50 150 v bias = 2.5v v en = 0v output current (a) 0 bias pin current (ma) 6 8 10 4 3071 g14 42 5 7 93 1 0 1 2 3 5 v out = 1.8v v bias = 3.3v v out = 0.8v v bias = 2.5v v in = v out + 300mv t j = 25c temperature (c) ?75 uvlo threshold voltage (v) 1.5 2.0 2.5 125 3071 g15 1.0 0.5 0 ?50 ?25 0 25 50 75 100 150 175 v bias rising v bias falling temperature (c) ?75 pwrgd treshold voltage (v) 0.90 0.95 125 3071 g17 0.850.80 ?25 25 50 175 1.00 v out falling 75 ?50 0 150 100 v bias = 2.5v v out = 1v v out rising temperature (c) ?75 pwrgd v ol voltage (mv) 60 80 100 125 3071 g18 40 20 0 ?25 25 75 ?50 0 50 100 175 150 v bias = 2.5v i pwrgd = 200a i mon vs i out output current (a) 0 0 i mon (ma) 0.5 1.0 1.5 2.0 2.5 1 2 3 4 3071 g16 5 6 v bias = 3.3v v out = 0.8v to 1.8v v in ? v out = 300mv t j = ?55c to 125c downloaded from: http:///
lt 3071 7 3071fc for more information www.linear.com/lt3071 en pin thresholds en pin threshold and hysteresis vs v bias typical performance characteristics sense pin current logic input threshold voltages logic low to hi-z state transitions logic pin input current,high state en pin logic high current logic input threshold voltages logic hi-z to high state transitions logic pin input current,low state sense pin current temperature (c) ?75 enable pin threshold (v) 1.2 1.6 2.0 125 3071 g19 0.80.4 1.0 1.4 1.80.6 0.2 0 ?25 ?50 25 0 75 100 150 50 175 v bias = 2.5v en pin rising en pin falling temperature (c) ?75 logic input threshold voltage (v) 0.6 0.7 0.8 125 3071 g21 0.5 0.4 0.3 ?50 ?25 0 25 50 75 100 150 175 input rising logic low to hi-z input falling logic hi-z to low see applications informationfor more details temperature (c) ?75 logic input threshold voltage (v) 2.8 2.9 3.0 125 3071 g22 2.7 2.6 2.5 ?50 ?25 0 25 50 75 100 150 175 input falling logic high to hi-z input rising logic hi-z to high v bias = 3.3v logic hi-z to high threshold is relative to v bias voltage see applications informationfor more details temperature (c) ?75 en pin logic high current (a) 4.0 5.0 6.0 125 3071 g23 3.02.0 3.5 4.5 5.52.5 1.5 1.0 ?25 ?50 25 0 75 100 150 50 175 v en = v bias = 2.5v temperature (c) ?75 logic pin input current (a) 4035 30 25 20 15 10 50 125 3071 g24 ?25 25 75 175 100 ?50 0 50 150 v logic = v bias = 2.5v current flows into the pin temperature (c) ?75 logic pin input current (a) 4035 30 25 20 15 10 50 125 3071 g25 ?25 25 75 175 100 ?50 0 50 150 v bias = 2.5v v logic = 0v current flows out of the pin temperature (c) ?75 sense pin current (a) 6560 55 50 45 40 35 30 25 125 3071 g26 ?25 25 75 175 100 ?50 0 50 150 v bias = 2.5v v out = 0.8v current flows into sense temperature (c) ?75 sense pin current (a) 400375 350 325 300 275 250 225 200 125 3071 g27 ?25 25 75 175 100 ?50 0 50 150 v bias = 3.3v v out = 1.8v current flows into sense bias voltage (v) 4.03.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3071 g20 t j = ?55?c to 125c 2 2.5 3 3.5 4 enable/disable threshold (v) v bias max enable typ enable typ disable min disable typical hysteresis = 150mv downloaded from: http:///
lt 3071 8 3071fc for more information www.linear.com/lt3071 typical performance characteristics bias pin ripple rejection in pin ripple rejection in pin ripple rejection frequency (hz) 10 100 40 bias pin ripple rejection (db) 50 60 70 80 1k 10k 100k 1m 10m 3071 g30 30 2010 0 90 100 v bias = 2.5v + 500mv p-p v bias = 2.7v + 500mv p-p v bias = 3.3v + 500mv p-p v in = 1.3v v out = 1v i out = 5a c out = 10f + 4.7f + 2.2f frequency (hz) 10 100 in pin ripple rejection (db) 40 50 60 1k 10k 100k 1m 10m 3071 g31 30 2010 0 70 80 c out = 117f c out = 16.9f v out = 1v v in = 1.3v + 50mv p-p ripple v bias = 2.5v i out = 1a frequency (hz) 10 100 in pin ripple rejection (db) 40 50 60 1k 10k 100k 1m 10m 3071 g32 30 2010 0 70 80 c out = 117f c out = 16.9f v out = 1v v in = 1.3v + 50mv p-p ripple v bias = 2.5v i out = 5a current limit vs v in ? v out in-to-out voltage differential (v) 0 current limit (a) 4 6 2.00 3071 g29 20 0.50 1.00 1.50 0.25 0.75 1.25 1.75 83 51 7 v out = 1.8v v out = 1.2v v out = 0.8v v bias = 3.3v t j = 25c current limit vs temperature temperature (c) ?75 current limit (a) 7.507.25 7.00 6.75 6.50 6.25 6.00 5.75 5.50 5.25 5.00 125 3071 g28 ?25 25 75 175 100 ?50 0 50 150 v in = v out(nominal) + 300mv v out = 1.8v, v bias = 3.3v v out = 1.2v, v bias = 3.3v v out = 0.8v, v bias = 2.5v average input/output differential (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 70 80 90 100 110 120 psrr (db) vs v in ? v out , 1v/5a in pin ripple rejection 3071 g33 50mv p-p ripple on v in c out = 16.9f v bias = 2.5v t a = 25c ripple at f = 10khz ripple at f = 100khz ripple at f = 1mhz average input/output differential (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 70 80 90 100 110 120 psrr (db) vs v in ? v out , 1v/2.5a in pin ripple rejection 3071 g34 50mv p-p ripple on v in c out = 16.9f v bias = 2.5v t a = 25c ripple at f = 10khz ripple at f = 100khz ripple at f = 1mhz average input/output differential (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 70 80 90 100 110 120 psrr (db) vs v in ? v out , 1v/1a in pin ripple rejection 3071 g35 50mv p-p ripple on v in c out = 16.9f v bias = 2.5v t a = 25c ripple at f = 10khz ripple at f = 100khz ripple at f = 1mhz average input/output differential (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 70 80 90 100 110 120 psrr (db) vs v in ? v out , 1v/5a in pin ripple rejection 3071 g36 50mv p-p ripple on v in c out = 117f v bias = 2.5v t a = 25c ripple at f = 10khz ripple at f = 100khz ripple at f = 1mhz downloaded from: http:///
lt 3071 9 3071fc for more information www.linear.com/lt3071 minimum bias voltage vs temperature minimum bias voltage vs v out minimum bias voltage vs i out load regulation temperature (c) ?75 minimum bias voltage (v) 3.2 3.6 4.0 125 3071 g39 2.82.4 3.0 3.4 3.82.6 2.2 2.0 ?25 ?50 25 0 75 100 150 50 175 i out = 5a v out = 1.8v v out = 1.2v v out = 0.8v output current (a) 0 minimum bias voltage (v) 2.6 2.8 3.0 3 5 3071 g40 2.4 2.2 2.0 1 2 4 3.2 3.4 3.6 v out = 1.8v v out = 1.5v v out = 1.2v v out = 0.8v to 1v v in = v out(nominal) + 300mv ? v out = ?1%, t j = 25c output voltage (v) 0.7 minimum bias voltage (v) 3.43.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.5 3071 g41 0.9 1.1 1.3 1.9 1.7 i out = 5a t j = 25c temperature (c) ?75 load regulation (mv) ?4 ?2 0 125 3071 g42 ?6 ?8 ?10 ?50 ?25 0 25 50 75 100 150 175 v in = v out(nominal) + 300mv v bias = 3.3v ? i out = 100ma to 5a v out = 0.8v v out = 1.2v v out = 1.8v typical performance characteristics average input/output differential (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 70 80 90 100 110 120 psrr (db) vs v in ? v out , 1v/2.5a in pin ripple rejection 3071 g37 50mv p-p ripple on v in c out = 117f v bias = 2.5v t a = 25c ripple at f = 10khz ripple at f = 100khz ripple at f = 1mhz average input/output differential (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 70 80 90 100 110 120 psrr (db) vs v in ? v out , 1v/1a in pin ripple rejection 3071 g38 50mv p-p ripple on v in c out = 117f v bias = 2.5v t a = 25c ripple at f = 10khz ripple at f = 100khz ripple at f = 1mhz bias voltage line regulation temperature (c) ?75 bias voltage line regulation (v) 800700 600 500 400 300 200 100 0 125 3071 g43 ?25 25 75 175 100 ?50 0 50 150 v bias = 2.2v to 3.6v v in = 1.1v v out = 0.8v i out = 10ma bias voltage line regulation input voltage line regulation temperature (c) ?75 bias voltage line regulation (v) 400300 200 100 0 ?100?200 ?300 ?400 125 3071 g44 ?25 25 75 175 100 ?50 0 50 150 v bias = 3.25v to 3.6v v in = 2.1v v out = 1.8v i out = 10ma temperature (c) 0 input voltage line regulation (v) 100 200 300 50 150 250 ?25 25 75 125 3071 g45 175 ?50 ?75 0 50 100 150 v bias = 3.3v v in = 1.05v to 2.7v v out = 0.8v i out = 10ma downloaded from: http:///
lt 3071 10 3071fc for more information www.linear.com/lt3071 typical performance characteristics rms output noise vs output current output noise (10hz to 100khz) input voltage line regulation output voltage start-up time vs c ref/byp output noise spectral density nap mode recovery time vs i out temperature (c) 0 input voltage line regulation (v) 100 200 300 50 150 250 ?25 25 75 125 3071 g46 175 ?50 ?75 0 50 100 150 v bias = 3.3v v in = 2.05v to 2.7v v out = 1.8v i out = 10ma ref/byp capacitance (f) 0 output voltage start-up time (ms) 12 16 20 0.4 3071 g47 84 10 14 18 62 0 0.1 0.2 0.3 0.5 v bias = 2.5v to 3.3v i out = 10ma c out = 10f + 4.7f + 2.2f t j = 25c see applicationsinformation for start-up details output current (a) 0 nap mode recovery time (s) 150 200 250 3 5 3071 g48 100 50 0 1 2 4 300 350 400 v bias = 3.3v v in = v out(nom) + 300mv en = low to highi out = 5a (set by a resistor load) t j = 25c v out = 1.8v, c out = 117f v out = 1.2v, c out = 117f v out = 0.8v, c out = 117f frequency (hz) 0.01 noise spectral density (v / hz ) 0.1 10 1k 10k 100k 3071 g49 0.001 100 1.0 v bias = 2.5v v out = 1v i out = 5a c out = 16.9f c ref/byp = 0.01f output current (a) 0.01 40 output noise (v rms ) 60 80 0.1 1 10 3071 g50 20 30 50 70 10 0 v in = v out(nominal) + 300mv v bias = 3.3v c out = 16.9f v out = 1.8v v out = 1.2v v out = 0.8v v out 100v/div 1ms/div v out = 1v i out = 5a c out = 16.9f 3071 g51 bias voltage line transient response vioc amplifier in-to-out servo voltage v out 10mv/div v bias 200mv/div 20s/div v in = 1.3v v bias = 2.5v v out = 1v i out = 5a c out = 16.9f 3071 g53 temperature (c) ?75 vioc in-to-out servo voltage (mv) 310 330 350 125 3071 g54 290270 300 320 340280 260 250 ?25 ?50 25 0 75 100 150 50 175 v bias = 2.5v input voltage line transient response v out 1mv/div v in 50mv/div 20s/div v in = 1.3v v out = 1v i out = 5a c out = 16.9f 3071 g52 downloaded from: http:///
lt 3071 11 3071fc for more information www.linear.com/lt3071 typical performance characteristics vioc amplifier output current vs temperature transient load response transient load response transient load response transient load response temperature (c) 150 vioc amplifier output current (a) 200 250 300175 225 275 ?25 25 75 125 3071 g55 175 ?50 ?75 0 50 100 150 i vioc sourcing i vioc sinking v out 50mv/div ac-coupled i out 2a/div ?i = 500ma to 5a 20s/div v out = 1v c out = 10f + 4.7f + 2.2f i out t rise /t fall = 100ns 3071 g56 v out 50mv/div ac-coupled i out 2a/div ?i = 500ma to 5a 20s/div v out = 1v c out = 117f i out t rise /t fall = 100ns 3071 g57 v out 50mv/div ac-coupled i out 2a/div ?i = 500ma to 5a 20s/div v out = 1v c out = 10f + 4.7f + 2.2f i out t rise /t fall = 1s 3071 g58 v out 50mv/div ac-coupled i out 2a/div ?i = 500ma to 5a 20s/div v out = 1v c out = 117f i out t rise /t fall = 1s 3071 g59 downloaded from: http:///
lt 3071 12 3071fc for more information www.linear.com/lt3071 pin functions vioc ( pin 1): voltage for in - to - out control. the ic incorpo - rates a unique tracking function to control a buck regulator powering the lt3071s input. the vioc pin is the output of this tracking function that drives the buck regulator to maintain the lt3071s input voltage at v out + 300 mv. this function maximizes efficiency and minimizes power dissipation. see the applications information section for more information on proper control of the buck regulator. pwrgd ( pin 2): power good. the pwrgd pin is an open- drain nmos output that actively pulls low if any one of these fault modes is detected: ? v out is less than 90% of v out(nominal) on the rising edge of v out . ? v out drops below 85% of v out(nominal) for more than 25s. ? junction temperature typically exceeds 145c. ? v bias is less than its undervoltage lockout threshold. ? the out-to-in reverse-current detector activates. see the applications information section for more infor - mation on pwrgd fault modes. ref/byp ( pin 3): reference filter. the pin is the output of the bandgap reference and has an impedance of ap - proximately 19 k. this pin must not be externally loaded. bypassing the ref/byp pin to gnd with a 10 nf capacitor decreases output voltage noise and provides a soft-start function to the reference. lt c recommends the use of a high quality, low leakage capacitor. see the applications information section for more information on noise and output voltage margining considerations. gnd ( pins 4, 9-14, 20, 26, exposed pad pin 29): ground. the exposed pad of the qfn package is an electrical con - nection to gnd. to ensure proper electrical and thermal performance, solder pin 29 to the pcb ground and tie to all gnd pins of the package. these gnd pins are fused to the internal die attach paddle and the exposed pad to optimize heat sinking and thermal resistance characteris - tics. see the applications information section for thermal considerations and calculating junction temperature. in ( pins 5, 6, 7, 8): input supply. these pins supply power to the high current pass transistor. tie all in pins together for proper performance. the lt3071 requires a bypass capacitor at in to maintain stability and low input impedance over frequency. a 47 f input bypass capacitor suffices for most battery and power plane impedances. minimizing input trace inductance optimizes performance . applications that operate with low v in -v out differential voltages and t hat have large, fast load transients may require much higher input capacitor requirements to prevent the input supply from drooping and allowing the regulator to enter dropout. see the applications information section for more information on input capacitor requirements. out ( pins 15, 16, 17, 18): output. these pins supply power to the load. tie all out pins together for proper performance. a minimum output capacitance of 15 f is required for stability. lt c recommends low esr, x5r or x7r dielectric ceramic capacitors for best performance. a parallel ceramic capacitor combination of 10 f + 4.7 f + 2.2 f or 15 1 f ceramic capacitors in parallel provide excellent stability and load transient response. large load transient applications require larger output capacitors to limit peak voltage transients. see the applications infor - mation section for more information on output capacitor requirements. sense ( pin 19): kelvin sense for out . the sense pin is the inverting input to the error amplifier. optimum regu - lation is o btained when the sense pin is connected to the out pins of the regulator. in critical applications, the resistance ( r p ) of pcb traces between the regulator and the load cause small voltage drops, creating a load regulation error at the point of load. connecting the sense pin at the load instead of directly to out eliminates this voltage error. figure 1 illustrates this kelvin - sense connection method. note that the voltage drop across the external pcb traces adds to the dropout voltage of the regulator . the sense pin input bias current depends on the selected output voltage. sense pin input current varies from 50 a typically at v out = 0.8 v to 300 a typically at v out = 1.8 v. downloaded from: http:///
lt 3071 13 3071fc for more information www.linear.com/lt3071 pin functions i mon ( pin 21): output current monitor. the i mon pin sources a current typically equal to i out /2500 or 400 a per amp of output current. terminating this pin with a resistor to gnd produces a voltage proportional to i out . for example, at i out = 5 a, i mon typically sources 2 ma. with a 1 k resistor to gnd, this produces 2 v. if i mon is unused, tie this pin to v bias . marga ( pin 22): analog margining. this pin margins the output voltage over a continuous analog range of 10%. tying this pin to gnd adjusts output voltage by C10%. driving this pin to 1.2 v adjusts output voltage by +10%. a voltage source or a voltage output dac is ideal for driving this pin. if the marga function is not used, either float this pin or terminate with a 1nf capacitor to gnd.v o0 , v o1 and v o2 ( pins 23, 24, 25): output voltage se- lect. these three-state pins combine to select a nominal output voltage from 0.8 v to 1.8 v in increments of 50 mv. output voltage is limited to 1.8 v maximum by an internal override of v o1 when v o2 = high . the input logic low threshold is less than 250 mv referenced to gnd and the logic high threshold is greater than v bias C 250 mv. the range between these two thresholds as set by a window comparator defines the logic hi-z state. see table 1 in the applications information section that defines the v o2 , v o1 and v o0 settings versus v out . bias ( pin 27): bias supply. this pin supplies current to the internal control circuitry and the output stage driving the pass transistor. the lt3071 requires a minimum 2.2 f bypass capacitor for stability and proper operation. to ensure proper operation, the bias voltage must satisfy the following conditions : 2.2 v v bias 3.6 v and v bias (1.25 ? v out + 1 v). for v out 0.95 v, the minimum bias voltage is limited to 2.2v.en ( pin 28): enable. this pin enables/disables the output device only. the internal reference and all support functions are active if v bias is above its uvlo threshold. pulling en low keeps the reference circuit active, but disables the output pass transistor and puts the lt3071 into a low power nap mode. the maximum rising en threshold is ratioed to 0.56% of v bias and the minimum falling enx threshold is 0.36% of v bias . drive the en pin with either a digital logic port or an open-collector npn or an open- drain nmos terminated with a pull-up resistor to v bias . the pull-up resistor must be less than 35 k to meet the v ih condition of the en pin. if unused, connect en to bias. figure 1. kelvin sense connection bias lt3071 enin v o0 v o1 v bias v in v o2 margavioc sense pwrgd out i mon r p ref/byp gnd + + r p 3071 f01 load downloaded from: http:///
lt 3071 14 3071fc for more information www.linear.com/lt3071 block diagram C + C + C + eamp ref/byp i sense buf ldo core out i mon 19 21 sense 2 pwrgd 3 28 1 ref/byp 600mv 3070 bd en vioc in 27 bias5-8 v out(nom) + 300mv 25 v o2 24 v o1 23 v o0 22 marga 15-18 detect v ref program control uvlo and thermal shutdown +C gnden 4,9-14,20,26,29 v bias C 0.25v v bias C 0.9v 0.75v 100k v o2 , v o1 , v o0 0.25v logic high state logic low state logic high state high if in < v bias C 0.9v and in > 0.75vhigh if in < 0.25v to logic high if in > v bias C 0.25v C +C + C + 500k to internal enable(see enable threshold curve) C + 100k v bias 28 downloaded from: http:///
lt 3071 15 3071fc for more information www.linear.com/lt3071 applications information introduction current generation fpga and asic processors place stringent demands on the power supplies that power the core, i/o and transceiver channels. these microprocessors may cycle load current from near zero to amps in tens of nanoseconds. output voltage specifications, especially in the 1 v range, require tight tolerances including transient response as part of the requirement. some asic processors require only a single output voltage from which the core and i/o circuitry operate. some high performance fpga processors require separate power supply voltages for the processor core, the i/o, and the transceivers. often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. these requirements mandate the need for very accurate, low noise, high cur - rent, very high speed regulator circuits that operate at low input and output voltages. the lt3071 is a low voltage, ultrafast transient response linear regulator. the device supplies up to 5 a of output current with a typical dropout voltage of 85 mv. a 0.01 f reference bypass capacitor decreases output voltage noise to 25 v rms ( bw = 10 hz to 100 khz). the lt3071s high bandwidth provides ultrafast transient response using low esr ceramic output capacitors (15 f minimum), saving bulk capacitance, pcb area and cost. th e lt3071 s features permit state - of - the - art linear regula - tor performance. the lt3071 is ideal for high performance fpgas, microprocessors, sensitive communication sup- plies, and high current logic applications that also operate over low input and output voltages. output voltage for the lt3071 is digitally selectable in 50mv increments over a 0.8 v to 1.8 v range. an analog margining function allows the user to adjust system output voltage over a continuous 10% range. the lt3071 provides an output current monitor that typically sources a current of i out /2500 or 400 a per amp of i out at its i mon pin. terminating the i mon pin to gnd with a resistor produces a voltage proportional to output current. this permits a user to measure system performance such as output power or if output current exceeds or falls below some threshold. the ic incorporates a unique tracking function, which if enabled by the user, controls an upsteam regulator power - ing the lt3071 s input ( see figure 8). this tracking function drives the buck regulator to maintain the lt3071s input voltage to v out + 300 mv. this input-to-output voltage control allows the user to change the regulator output voltage, and have the switching regulator powering the lt3071s input to track to the optimum input voltage with no component changes. this combines the efficiency of a switching regulator with superior linear regulator response. it also permits thermal management of the system even with a maximum 5a output load. lt3071 internal protection includes input undervoltage lockout ( uvlo), reverse - current protection, precision cur - rent limiting with power foldback and thermal shutdown. the lt3071 regulator is available in a thermally enhanced 28-lead, 4mm 5mm qfn package. the lt3071s architecture drives an internal n-channel power mosfet as a source follower. this configuration permits a user to obtain an extremely low dropout, ultra - fast transient response regulator with excellent high fre- quency psrr p erformance. the lt3071 achieves superior regulator bandwidth and transient load performance by eliminating expensive bulk tantalum or electrolytic capaci - tors in the most modern and demanding microprocessor applications. users realize significant cost savings as all additional bulk capacitance is removed. the additional savings of insertion cost, purchasing/inventory cost and board space are readily apparent. precision incremental output voltage control accommodates legacy and future microprocessor power supply voltages. output capacitor networks simplify to direct parallel com- binations of ceramic capacitors. often, the high frequency ceramic decoupling capacitors required by these various downloaded from: http:///
lt 3071 16 3071fc for more information www.linear.com/lt3071 applications information fpga and asic processors are sufficient to stabilize the system ( see stability and output capacitance section). this regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. the lt3071 also incorporates precision current limit - ing, enable/disable control of output voltage and inte- grated overvoltage and thermal shutdown protection. the lt3071s unique design combines the benefits of low dropout voltage, high functional integration, precision performance and ultrafast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. as lower voltage applications become increasingly preva - lent with higher frequency switching power supplies, the lt3071 offers superior regulation and an appreciable component cost savings. the lt3071 steps to the next level of performance for the latest generation fpgas, dsps and microprocessors. the simple versatility and benefits derived from these circuits exceed the power supply needs of todays high performance microprocessors. programming output voltage three tri-level input pins, v o2 , v o1 and v o0 , select the value of output voltage. table 1 illustrates the 3- bit digital word to output voltage resulting from setting these pins high , low or allowing them to float. these pins may be tied high or low by either pin-strapping them to v bias or driving them with digital ports. pins that float may either actually float or require logic that has hi-z output capability. this allows output voltage to be dynamically changed if necessary. output voltage is selectable from a minimum of 0.8 v to a maximum of 1.8 v in increments of 50 mv. the msb, v o2 , sets the pedestal voltage, and the lsbs, v o1 and v o0 increment v out . output voltage is limited to 1.8 v maximum by an internal override of v o1 (default to low ) when v o2 = high . table 1: v o2 to v o0 settings vs output voltage v o2 v o1 v o0 v out(nom) v o2 v o1 v o0 v out(nom) 0 0 0 0.80v z 0 1 1.35v 0 0 z 0.85v z z 0 1.40v 0 0 1 0.90v z z z 1.45v 0 z 0 0.95v z z 1 1.50v 0 z z 1.00v z 1 0 1.55v 0 z 1 1.05v z 1 z 1.60v 0 1 0 1.10v z 1 1 1.65v 0 1 z 1.15v 1 x 0 1.70v 0 1 1 1.20v 1 x z 1.75v z 0 0 1.25v 1 x 1 1.80v z 0 z 1.30v x = dont care, 0 = low, z = float, 1 = high the input logic low threshold is less than 250 mv refer- enced to gnd and the logic high threshold is greater than v bias C 250 mv. the range between these two thresholds as set by a window comparator defines the logic hi-z state. ref/byp?voltage reference this pin is the buffered output of the internal bandgap reference and has an output impedance of ? 19k. the design includes an internal compensation pole at f c = 4khz. a 10 nf ref/byp capacitor to gnd creates a low- pass pole at f lp = 840 hz. the 10 nf capacitor decreases reference voltage noise to about 10 v rms and soft-starts the reference. the lt3071 only soft-starts the reference voltage during an initial turn-on sequence. if the en pin is toggled low after initial turn-on, the reference remains powered-up. therefore, toggling the en pin from low to high does not soft-start the reference. only by turning the bias supply voltage on and off will the reference be soft-started. output voltage noise is the rms sum of the reference voltage noise in addition to the amplifier noise. the ref / byp pin must not be dc loaded by anything except for applications that parallel other lt3071 regulators for higher output currents. consult the applications section on paralleling for further details. downloaded from: http:///
lt 3071 17 3071fc for more information www.linear.com/lt3071 applications information output voltage margining the lt3071s analog margining pin, marga, provides a continuous output voltage adjustment range of 10%. it margins v out by adjusting the internal 600 mv reference voltage up and down. the marga pins typical input impedance is 190 k between marga and the internal v ref node. driving marga with 600 mv to 1.2 v provides 0% to 10% of adjustment. driving marga with 600 mv to 0v provides 0% to C10% of adjustment. if unused, allow marga to float or bypass this pin with a 1 nf capacitor to gnd. note that the analog margining function does not adjust the pwrgd threshold. therefore, negative analog margining may trip the pwrgd comparator and toggle the pwrgd flag. enable function?turning on and off the en pin enables/disables the output device only. the lt3071 reference and all support functions remain active if v bias is above its uvlo threshold. pulling the en pin low puts the lt3071 into nap mode. in nap mode, the reference circuit is active, but the output is disabled and quiescent current decreases. drive the en pin with either a digital logic port or an open- collector npn or an open-drain nmos terminated with a pull-up resistor to v bias . the pull-up resistor must be less than 35 k to meet the v ih condition of the en pin. if unused, connect en to bias. input undervoltage lockout on bias pin an internal undervoltage lockout ( uvlo) comparator monitors the bias supply voltage. if v bias drops below the uvlo threshold, all functions shut down, the pass transistor is gated off and output current falls to zero. the typical bias pin uvlo threshold is 1.55 v on the rising edge of v bias . the uvlo circuit incorporates about 150 mv of hysteresis on the falling edge of v bias . high efficiency linear regulator?input-to-output voltage control the vioc (voltage input-to-output control) pin is a func - tion to control a switching regulator and facilitate a design solution that maximizes system efficiency at high load cur- rents and still provides low dropout voltage performance. the vioc pin is the output of an integrated transcon- ductance amplifier that sources and sinks about 250 a of current. it typically regulates the output of most lt c ? switching regulators or lt m ? power modules, by sinking current from the ith compensation node. the vioc function controls a buck regulator powering the lt3071s input by maintaining the lt3071s input voltage to v out + 300 mv. this 300 mv v in -v out differential voltage is chosen to provide fast transient response and good high frequency psrr while minimizing power dissipation and maximizing efficiency. for example , 1.5 v to 1.2 v conversion and 1.3 v to 1 v conversion yield 1.5 w maximum power dissipation at 5a full output current.figure 2 depicts that the switchers feedback resistor net - work sets the maximum switching regulator output voltage if the linear regulator is disabled. however, once the lt3071 is enabled, the vioc feedback loop decreases the switching regulator output voltage back to v out + 300 mv. using the vioc function creates a feedback loop between the lt3071 and the switching regulator. as such, the feedback loop must be frequency compensated for sta - bility. fortunately, the connection of vioc to many lt c switching regulator ith pins represents a high impedance characteristic which is the optimum circuit node to fre - quency compensate the feedback loop. figure 2 illustrates the typical frequency compensation network used at the vioc node to gnd. the vioc amplifier characteristics are: g m = 3.2ms, i out = 250a, bw = 10mhz. if the vioc function is not used, terminate the vioc pin to gnd with a small capacitor (1000 pf) to prevent oscillations. downloaded from: http:///
lt 3071 18 3071fc for more information www.linear.com/lt3071 applications information figure 2. vioc control block diagram pwrgd?power good pwrgd pin is an open-drain nmos digital output that actively pulls low if any one of these fault modes is detected : ? v out is less than 90% of v out(nominal) on the rising edge of v out . ? v out drops below 85% of v out(nominal) for more than 25s. ? v bias is less than its undervoltage lockout threshold. ? the out-to-in reverse-current detector activates. ? junction temperature exceeds 145c typically.* * the junction temperature detector is an early warning indicator that trips approximately 20 c before thermal shutdown engages. stability and output capacitance the lt3071s feedback loop requires an output capacitor for stability. choose c out carefully and mount it in close proximity to the lt3071 s out and gnd pins. include wide routing planes for out and gnd to minimize inductance. if possible, mount the regulator immediately adjacent to the application load to minimize distributed inductance for optimal load transient performance. point - of - load applica - tions present the best case layout scenario for extracting full lt3071 performance. low esr, x5r or x7r ceramic chip capacitors are the lt c recommended choice for stabilizing the lt3071. ad- ditional bulk capacitors distributed beyond the immediate decoupling capacitors are acceptable as their parasitic esl and esr, combined with the distributed pcb inductance isolates them from the primary compensation pole provided by the local surface mount ceramic capacitors. the lt3071 requires a minimum output capacitance of 15 f for stability. lt c strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. why do multiple, small-value output capacitors connected in parallel work better? the lt3071s unity-gain bandwidth with c out of 15 f is about 1 mhz at its full-load current of 5 a. surface mounted mlcc capacitors have a self-resonance frequency of f r = 1/(2 lc ), which must be pushed to a frequency higher than the regulator bandwidth. standard mlcc capacitors are acceptable. to keep the resonant frequency greater than 1 mhz, the product 1/(2 lc ) must be greater than 1mhz. at this bandwidth, pcb vias can add significant inductance, thus the fundamental decoupling capacitors must be mounted on the same plane as the lt3071. reference lt3071 in v ref v out + 300mv out vioc 3071 f02 load +C pwm switching regulator ref fb i th downloaded from: http:///
lt 3071 19 3071fc for more information www.linear.com/lt3071 applications information typical 0603 or 0805 case-size capacitors have an esl of ~800ph and pcb mounting can contribute up to ~200 ph. thus, it becomes necessary to reduce the parasitic in - ductance by using a parallel capacitor combination. a suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, f r , will form a tank circuit that can induce ringing of their own accord. small amounts of esr (5 m to 20 m ) have some benefit in dampening the resonant loop, but higher esrs degrade the capacitor response to transient load steps with rise/fall times less than 1 s. the most area efficient parallel capacitor combination is a graduated 4/2/1 scale of f r of the same case size. under these conditions, the individual esls are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. the recommended parallel combination that approximates 15 f is 10 f + 4.7 f + 2.2 f. capacitors with case sizes larger than 0805 have higher esl and lower esr (<5 m). therefore, more capacitors with smaller values (<10 f) must be chosen. users should consider new generation, low inductance capacitors to push out f r and maximize stability. refer to the surface mount ceramic capacitor manufacturers data sheets for capacitor specifications. figure 3 illustrates an optimum pcb layout for the parallel output capacitor combination, but also illustrates the gnd connection between the in capacitor and the out capacitors to minimize the ac gnd loop for fast load transients. this tight bypassing connection minimizes emi and optimizes bypassing. many of the applications in which the lt3071 excels, such as fpga, asic processor or dsp supplies, typically require a high frequency decoupling capacitor network for the device being powered. this network generally consists of many low value ceramic capacitors in parallel. in some applications, this total value of capacitance may be close to the lt3071s minimum 15 f capacitance requirement. this may reduce the required value of capacitance directly at the lt3071s output. multiple low value capacitors in parallel present a favorable frequency characteristic that pushes many of the parasitic poles/zeroes beyond the lt3071s unity-gain crossover frequency. this technique illustrates the method that extracts the full bandwidth performance of the lt3071. give additional consideration to the use of ceramic capaci - tors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are specified with eia temperature characteristic codes of z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small pack - age, but they tend to have strong voltage and temperature coefficients as shown in figures 4 and 5. when used with a 5 v regulator, a 16 v 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2 f for the dc bias voltage applied and over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. figure 3. example pcb layout 2.2f4.7f 10f 47f 3071 f03 low-z input load plane lt3071 sense in out gnd downloaded from: http:///
lt 3071 20 3071fc for more information www.linear.com/lt3071 applications information the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. care still must be exercised when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias with x5r and x7r capacitors is better than y5v and z5u capacitors, but can still be significant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as component case size increases, but expected capacitance at operat - ing voltage should be verified. voltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezo - electric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric microphone works. for a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. stability and input capacitance the lt3071 is stable with a minimum capacitance of 47f connected to its in pins. use low esr capacitors to minimize instantaneous voltage drops under large load transient conditions. large v in droops during large load transients may cause the regulator to enter dropout with corresponding degradation in load transient response. increased values of input and output capacitance may be necessary depending on an applications requirements. sufficient input capacitance is critical as the circuit is in - tentionally operated close to dropout to minimize power. ideally, the output impedance of the supply that powers in should be less than 10 m to support a 5 a load with large transients. in cases where wire is used to connect a power supply to the input of the lt3071 ( and also from the ground of the lt3071 back to the power supply ground), large input capacitors are required to avoid an unstable application. this is due to the inductance of the wire forming an lc tank circuit with the input capacitor and not a result of the lt3071 being unstable. the self inductance, or isolated inductance, of a wire is directly proportional to its length. however, the diameter of a wire does not have a major influence on its self inductance. for example, one inch of 18- awg , 0.04 inch diameter wire has 28 nh of self induc - tance. the self inductance of a 2- awg isolated wire with a diameter of 0.26 inch is about half the inductance of a 18- awg wire. the overall self inductance of a wire can be reduced in two ways. one is to divide the current flowing towards the lt3071 between two parallel conductors which flows in the same direction in each. in this case, the farther the wires are placed apart from each other, the more inductance will be reduced, up to a 50% reduction when placed a few inches apart. splitting the wires basi - cally connects two equal inductors in parallel. however, when placed in close proximity from each other, mutual inductance is added to the overall self inductance of the dc bias voltage (v) 0 ?100 change in value (%) ?80 ?60 ?40 ?20 4 8 12 16 3071 f04 0 20 2 6 10 x5r y5v 14 both capacitors are 16v,1210 case size, 10f temperature (c) C50 C20 0 40 25 75 x5r y5v 3071 f05 C40C60 C25 0 50 100 125 C80 C100 20 change in value (%) both capacitors are 16v,1210 case size, 10f figure 4. ceramic capacitor dc bias characteristics figure 5. ceramic capacitor temperature characteristics downloaded from: http:///
lt 3071 21 3071fc for more information www.linear.com/lt3071 applications information wires. the most effective way to reduce overall inductance is to place the forward and return-current conductors ( the wire for the input and the wire for the return ground) in very close proximity. tw o 18- awg wires separated by 0.05 inch reduce the overall self inductance to about one- fourth of a single isolated wire. if the lt3071 is powered by a battery mounted in close proximity with ground and power planes on the same circuit board, a 47 f input capacitor is sufficient for stability. however, if the lt3071 is powered by a distant supply, use a low esr, large value input capacitor on the order of 330 f. as power supply output impedance varies, the minimum input capacitance needed for application stability also varies.bias pin capacitance requirements the bias pin supplies current to most of the internal control circuitry and the output stage driving the pass transistor. the lt3071 requires a minimum 2.2 f bypass capacitor for stability and proper operation. to ensure proper operation, the bias voltage must sat - isfy the following conditions : 2.2 v v bias 3.6 v and v bias (1.25 ? v out + 1 v). for v out 0.95 v, the minimum bias voltage is limited to 2.2v. load regulation the lt3071 provides a kelvin sense pin for v out , allowing the application to correct for parasitic package and pcb i-r drops. however, lt c recommends that the sense pin terminate in close proximity to the lt3071s out pins . this minimizes parasitic inductance and optimizes regula - tion. the lt3071 handles moderate levels of output line impedance, but excessive impedance between v out and c out causes excessive phase shift in the feedback loop and adversely affects stability.figure 1 in the pin functions section illustrates the kelvin- sense connection method that eliminates voltage drops due to pcb trace resistance. however, note that the voltage drop across the external pcb traces adds to the dropout voltage of the regulator. the sense pin input bias current depends on the selected output voltage. sense pin input current varies from 50 a typically at v out = 0.8 v to 300 a typically at v out = 1.8v. short-circuit and overload recoverylike many ic power regulators, the lt3071 has safe op- erating area ( soa) protection. the safe area protection decreases current limit as input - to - output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage up to the absolute maximum voltage rating. v bias must be above the uvlo threshold for any function. the lt3071 has a precision current limit specified at 20% that is active if v bias is above uvlo. under conditions of maximum i load and maximum v in -v out the devices power dissipation peaks at about 3w. if ambient temperature is high enough, die junction temperature will exceed the 125 c maximum operating temperature. if this occurs, the lt3071 relies on two additional thermal safety features. at about 145 c, the pwrgd output pulls low providing an early warning of an impending thermal shutdown condition. at 165 c typically , the lt3071s thermal shutdown engages and the output is shut down until the ic temperature falls below the thermal hysteresis limit. the soa protection decreases current limit as the in-to-out voltage increases and keeps the power dissipation at safe levels for all values of input-to-output voltage. the lt3071 provides some output current at all values of input-to-output voltage up to the absolute maxi - mum voltage rating. see the current limit vs v in curve in the typical performance characteristics. during start - up, after the bias voltage has cleared its uvlo threshold and v in is increasing, output voltage increases at the rate of current limit charging c out . with a high input voltage, a problem can occur where the removal of an output short will not allow the output voltage to recover. other regulators with current limit foldback also exhibit this phenomenon, so it is not unique to the lt3071. the load line for such a load may intersect the output current curve at two points: normal operation and the soa restricted load current settings. a common situ - ation is immediately after the removal of a short circuit, but with a static load 1 a. in this situation, removal of the load or reduction of i out to <1 a will clear this condition and allow v out to return to normal regulation. downloaded from: http:///
lt 3071 22 3071fc for more information www.linear.com/lt3071 applications information reverse voltage the lt3071 incorporates a circuit that detects if v in decreases below v out . this reverse-voltage detector has a typical threshold of about ( v in C v out ) = C6 mv. if the threshold is exceeded, this detector circuit turns off the drive to the internal nmos pass transistor, thereby turning off the output. the output pulls low with the load current discharging the output capacitance. this circuits intent is to limit and prevent back-feed current from out to in if the input voltage collapses due to a fault or overload condition. it should be noted that a negative ( ? ) reverse detection threshold implies that a small back-feed cur - rent can flow from v out to v in , as long as the dut is enabled. to guarantee shutdown the enable ( en) pin must be pulled low.thermal considerations the lt3071s maximum rated junction temperature of 125c limits its power handling capability and is domi - nated by the output current multiplied by the input/output voltage differential: i out ? (v in C v out ) the lt3071s internal power and thermal limiting circuitry protect it under overload conditions. for continuous nor- mal load conditions, do not exceed the maximum junction temperature of 125 c. give careful consideration to all sources of thermal resistance from junction to ambient. this includes junction to case, case-to-heat sink interface, heat sink resistance or circuit board to ambient as the application dictates . also, consider additional heat sources mounted in proximity to the lt3071. the lt3071 is a surface mount device and as such, heat sinking is ac- complished by using the heat spreading capabilities of the pc board and its copper traces. surface mount heat sinks and plated through-holes can also be used to spread the heat generated by power devices. junction - to - case thermal resistance is specified from the ic junction to the bottom of the case directly below the die. this is the lowest resis - tance path for heat flow. proper mounting is required to ensure the best possible thermal flow from this area of the package to the heat sinking material. note that the exposed pad is electrically connected to gnd. t able 3 lists thermal resistance as a function of copper area in a fixed board size. all measurements were taken in still air on a 4- layer fr-4 board with 1 oz solid internal planes and 2 oz top/ bottom external trace planes with a total board thickness of 1.6 mm. pcb layers, copper weight , board layout and thermal vias affect the resultant thermal resistance. for further information on thermal resistance and high thermal conductivity test boards, refer to jedec standard jesd51, notably jesd51-12 and jesd51-7. achieving low thermal resistance necessitates attention to detail and careful pcb layout. table 3, ufd plastic package, 28-lead qfn copper area board area thermal resistance (junction-to-ambient) topside* back side 2500mm 2 2500mm 2 2500mm 2 30c/w 1000mm 2 2500mm 2 2500mm 2 32c/w 225mm 2 2500mm 2 2500mm 2 33c/w 100mm 2 2500mm 2 2500mm 2 35c/w *device is mounted on topside downloaded from: http:///
lt 3071 23 3071fc for more information www.linear.com/lt3071 applications information calculating junction temperature example: given an output voltage of 0.9 v, an input voltage range of 1.2v 5%, a bias voltage of 2.5v, a maximum output current of 4 a and a maximum ambient temperature of 50 c, what will the maximum junction temperature be? the power dissipated by the device equals: i out(max) ? ( v in(max) C v out ) + ( i bias C i gnd ) ? v out + i gnd ? v bias where: i out(max) = 4a v in(max) = 1.26v i bias at (i out = 4a, v bias = 2.5v) = 6.91ma i gnd at (i out = 4a, v bias = 2.5v) = 0.87ma thus: p = 4 a ? (1.26 v C 0.9 v ) + (6.91 ma C 0.87 ma ) ? 0.9 v + 0.87ma ? 2.5v = 1.448w with the qfn package soldered to maximum copper area, the thermal resistance is 30 c/w. so the junction temperature rise above ambient equals: 1.448 w at 30c/w = 43.44c the maximum junction temperature equals the maximum ambient temperature plus the maximum junction tempera - ture rise above ambient or: t jmax = 50c + 43.44c = 93.44c applications that cannot support extensive pcb space for heat sinking the lt3071 require a derating of output current or increased airflow. paralleling devices for higher i out multiple lt3071 s may be paralleled to obtain higher output current. this paralleling concept borrows from the scheme employed by the lt3080. to accomplish this paralleling, tie the ref/byp pins of the paralleled regulators together. this effectively gives an averaged value of multiple 600 mv reference voltage sources. tie the out pins of the paralleled regulators to the common load plane through a small piece of pc trace ballast or an actual surface mount sense resistor beyond the primary output capacitors of each regulator. the re - quired ballast is dependent upon the application output voltage and peak load current. the recommended ballast is that value which contributes 1% to load regulation. for example, two lt3071 regulators configured to output 1 v, sharing a 10 a load require 2 m of ballast at each output. the kelvin sense pins connect to the regulator side of the ballast resistors to keep the individual control loops from conflicting with each other ( see figures 8 and 9). keep this ballast trace area free of solder to maintain a controlled resistance. table 4 shows a simple guideline for pcb trace resistance as a function of weight and trace width. table 4. pc board trace resistance weight (oz) 100 mil width* 200 mil width* 1 5.43 2.71 2 2.71 1.36 *trace resistance is measured in milliohms/in downloaded from: http:///
lt 3071 24 3071fc for more information www.linear.com/lt3071 figure 6. 1.5v to 1.2v linear regulator applications information quieting the noise the lt3071 offers numerous noise performance advan- tages. each ldo has several sources of noise. an ldos most critical noise source is the reference, followed by the ldo error amplifier. traditional low noise regulators buffer the voltage reference out to an external pin ( usually through a large value resistor) to allow for bypassing and noise reduction of reference noise. the lt3071 deviates from the traditional voltage reference by generating a low voltage v ref from a reference current into an inter- nal resistor ? 19k. this intermediate impedance node ( ref / byp) facilitates external filtering directly. a 10 nf filter capacitor minimizes reference noise to 10 v rms at the 600mv ref/byp pin, equivalently a 17 v contribution to output noise at v out = 1 v. see the typical performance characteristics for noise vs output voltage performance as a function of c ref/byp . this approach also accommodates reference sharing between lt3071 regulators that are hooked up in cur - rent sharing applications. the ref/byp filter capacitor delays the initial power-up time by a factor of the rc time constant. v ref remains active in nap mode, thus start-up time is significantly reduced and well controlled coming out of nap mode (en:lo hi). bias 50k lt3071 inen v o0 v o1 330f 2.2f 2.2f* 0.01f 1k v mon 2v at 5a full scale 1nf nc 4.7f* 3071 f06 10f* *x5r or x7r capacitors pwrgd v out 1.2v5a v o2 marga i mon vioc sense out v bias 2.2v to 3.6v v in 1.5v pwrgd ref/byp gnd downloaded from: http:///
lt 3071 25 3071fc for more information www.linear.com/lt3071 applications information 0.1f 1 20k 10k 2k 4.7nf 47f6.3v 3 bias 50k lt3071 enin v o2 v o0 2.2f 47f 1.3v/5a 100f6.3v 2 2.2f* 0.01f notes: ltc3415 switcher, 2mhz internal oscillator ltc3415 and lt3071 on same pcb power plane 4.7f* 3070 f07 10f* pwrgd *x5r or x7r capacitors v out 1v5a v mon 2v at 5a full scale v o1 marga ncnc nc vioc sense out v bias 3.3v pwrgd ref/byp i mon gnd sgndpv in pv in plllpfclkout phmode clkin mode swsw sw sw i th mgn bsel v fb i thm sgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pv in pv in run pgood track 0.2h sv in sv in sv in nc ltc3415euhf 1nf 1k nc nc nc figure 7. regulator with vioc buck control downloaded from: http:///
lt 3071 26 3071fc for more information www.linear.com/lt3071 applications information figure 8. 1v, 7a point-of-load current sharing regulators 0.1f nc nc 1 47f6.3v 3 bias 50k lt3071 enin v o2 v o0 2.2f 2.2f 47f 47f 1nf 1.3v/7a 100f6.3v 2 nc 2.2f* 0.01f notes: ltc3415 switcher, 2mhz internal oscillator ltc3415 and lt3071 ( 2) on same pcb power plane 4.7f* 10f* pwrgd *x5r or x7r capacitors v out 1v3.5a v o1 marga nc ncnc vioc sense out v bias 3.3v pwrgd ref/byp i mon gnd bias lt3071 enin v o2 v o0 2.2f* 0.01f 715 1nf 4.7f* 3071 f08 10f* *x5r or x7r capacitors v out 1v3.5a v mon 2v at 7a full scale v o1 marga ncnc nc vioc sense out pwrgd ref/byp i mon gnd sgndpv in pv in plllpfclkout phmode clkin mode swsw sw sw i th mgn bsel v fb i thm sgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pv in pv in run pgood nc track 0.2h 17.5k1% sv in sv in ltc3415euhf 15k1% r trace 3mcontrolled p.o.l. 1 p.o.l. 2 r trace 3mcontrolled power plane 1v/7a downloaded from: http:///
lt 3071 27 3071fc for more information www.linear.com/lt3071 figure 9. triple output supply providing 1v, 8a and 1.8v, 5a and 1.5v, 3a applications information bias 50k lt3071 in env o0 v o1 47f 2.2f v in 3.3v 2.2f* 0.01f 1nf 4.7f* 10f* v mon 2v at 5a full scale v mon 2v at 3a full scale p.o.l. 1 p.o.l. 2 pwrgd v out 1v4a v o2 marga i mon nc nc nc vioc sense out pwrgd ref/byp gnd 10f v in 3.3v 10f v buck1 = 1.3v/8a v buck2 = 2.1v/8a 100f6.3v x5r 100f6.3v x5r v out1 mgn1 fb1 ith1 ithm1 bsel1 pgood1 v in1 sv in1 run1plllpf1 mode1 phmode1 track1 v in2 sv in2 run2plllpf2 mode2 phmode2 track2 v out2 mgn2 fb2 ith2 ithm2 bsel2 pgood2 gnd2 sgnd2 gnd1 sgnd1 sw2 nc clkout2 clkin2 clkout1 ltm4616 clkin1 sw1 nc nc nc nc nc 4.7nf 1nf r trace 2.5mcontrolled r trace 2.5mcontrolled note: the two ltm4616 module channels are independently controlled by the v ioc controls from the linear regulators 2k 10k 1nf 47f 4.7nf *x5r or x7r capacitors bias lt3071 in env o0 v o1 47f 20k 20k 10k 2k ncnc nc nc 2.2f 2.2f* 0.01f 620 1k 4.7f* 10f* v out 1v4a v mon 2v at 8a full scale v o2 marga i mon nc nc nc v ioc sense out pwrgd ref/byp gnd *x5r or x7r capacitors bias lt3071 in env o0 v o1 2.2f 2.2f* 0.01f 4.7f* 10f* v out 1.8v5a v o2 marga i mon nc nc nc v ioc sense out pwrgd ref/byp gnd *x5r or x7r capacitors bias lt3071 in env o0 v o1 47f 2.2f v in 3.3v v in 3.3v v in 3.3v 2.2f* 0.01f 1nf 4.7f* 10f* v out 1.5v3a v o2 marga i mon nc ncnc vioc sense out pwrgd ref/byp gnd *x5r or x7r capacitors 1.67k 3071 f09 power plane 1v/7a downloaded from: http:///
lt 3071 28 3071fc for more information www.linear.com/lt3071 package description ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 27 28 12 bottom viewexposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 downloaded from: http:///
lt 3071 29 3071fc for more information www.linear.com/lt3071 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 8/10 swapped in and en pins in figure 7 24 b 4/13 clarified parameters, conditions and notes in electrical characteristics table 3, 4 added new graph: en pin threshold and hysteresis vs v bias 7 clarified en pin operation 12 enhanced block diagram 13 c 2/15 added psrr curves 8, 9 modified reverse voltage section 22 downloaded from: http:///
lt 3071 30 3071fc for more information www.linear.com/lt3071 ? linear technology corporation 2012 lt 0215 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt3071 related parts part description comments lt1764 / lt1764a 3a, fast transient response, low noise ldo 340mv dropout voltage, low noise: 40v rms , v in : 2.7v to 20v, to-220 and dd packages a version stable also with ceramic caps lt1963 / lt1963a 1.5a low noise, fast transient response ldo 340mv dropout voltage, low noise: 40v rms , v in : 2.5v to 20v, a version stable with ceramic caps, to-220, dd, sot-223 and so-8 packages lt1965 1.1a, low noise, low dropout linear regulator 290mv dropout voltage, low noise: 40v rms , v in : 1.8v to 20v, v out : 1.2v to 19.5v, stable with ceramic caps, to-220, dd-pak, msop and 3mm 3mm dfn packages lt3021 500ma, low v oltage, vldo? linear regulator v in : 0.9v to 10v, dropout voltage = 160mv ( typ ), adjustable output (v ref = v out(min) = 200mv), fixed output voltages: 1.2v, 1.5v, 1.8v, stable with low esr, ceramic output capacitors 16-pin dfn (5mm 5mm) and 8-lead so packages lt3080 / lt3080-1 1.1a, parallelable, low noise, low dropout linear regulator 300mv dropout voltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1 resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, to-220, sot-223, msop-8 and 3mm 3mm dfn-8 packages; lt3080-1 has integrated internal ballast resistor lt3085 500ma, parallelable, low noise, low dropout linear regulator 275mv dropout v oltage (2-supply operation), low noise: 40v rms , v in : 1.2v to 36v, v out : 0v to 35.7v, current-based reference with 1 resistor v out set; directly parallelable (no op amp required), stable with ceramic caps, msop-8 and 2mm 3mm dfn-6 packages ltc3025-1 / ltc3025-2 / ltc3025-3 / ltc3025-4 500ma micropower vldo linear regulator in 2mm 2mm dfn v in = 0.9v to 5.5v, dropout voltage: 75mv, low noise 80v rms , low i q : 54a, fixed output: 1.2v (ltc3025-2), 1.5v (ltc3025-3), 1.8v (ltc3025 -4); adjustable output range: 0.4v to 3.6v (ltc3025-1) 2mm 2mm 6-lead dfn package ltc3026 1.5a, low input voltage vldo regulator v in : 1.14v to 3.5v (boost enabled), 1.14v to 5.5v (with external 5v), v do = 0.1v, i q = 950a, stable with 10f ceramic capacitors, 10-lead msop and dfn-10 packages lt3070 5a, low noise, programmable output, 85mv dropout linear regulator v in : 0.95v to 3v, v out : 0.8v to 1.8v in 50mv increments, low noise: 25v rms , stable with ceramic capacitors, 4mm 5mm 28-lead qfn package typical application 1.5v to 1.2v linear regulator bias 50k lt3071 inen v o0 v o1 330f 2.2f 2.2f* 0.01f 1k v mon 2v at 5a full scale 1nf nc 4.7f* 3071 ta02 10f* *x5r or x7r capacitors pwrgd v out 1.2v5a v o2 marga i mon vioc sense out v bias 2.2v to 3.6v v in 1.5v pwrgd ref/byp gnd downloaded from: http:///

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